1. Field of the Invention
The present invention relates to three-dimensional integrated circuit (3-D IC) devices of the type including at least one array area and an associated contact area, and in particular to providing enhanced electrical contact at the contact area between interlayer conductors, such as bit line plugs, and increasingly thin semiconductor or conductor active layers in a stack of alternating active and insulating layers.
2. Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in 3D architectures.
In one example, a 3D memory device includes a plurality of stacks of NAND strings of memory cells. The stacks include semiconductor strips, also referred to as active layers, separated by insulating layers. The 3D memory device includes an array including a plurality of word lines structures, a plurality of string select structures, and ground select lines, arranged orthogonally over the plurality of stacks. Memory cells including charge storage structures are formed at cross-points between side surfaces of the semiconductor strips in the plurality of stacks and the word line structures.